About VMM for SystemVerilog
The VMM methodology defines industry best practices for creating robust, reusable and scalable verification environments using SystemVerilog. Introduced in 2005, it is the industry's most widely used and proven verification methodology for SystemVerilog.
The VMM methodology enables verification novices and experts alike to develop powerful transaction-level, constrained-random verification environments. A comprehensive set of guidelines, recommendations and rules help engineers avoid common mistakes while creating interoperable verification components. The VMM Standard Library provides the foundation base classes for building advanced testbenches, while VMM Applications provide higher-level functions for improved productivity.
The Road to a Single Industry Standard
In 2008, user demand for a single, open standard for verification interoperability grew. Accellera, the industry group that originally created SystemVerilog, responded by forming a verification interoperability technical subcommittee to create relevant standards. Synopsys enthusiastically supported this initiative, and donated its complete implementation of the VMM methodology to Accellera to help speed the creation of a single, unified industry standard methodology.
The Origins of VMM
The SystemVerilog language introduced powerful new verification language constructs such as constraints, functional coverage and object-oriented programming. Recognizing that many engineers would require guidance on how to take advantage of these language features, ARM and Synopsys began a collaboration in 2004 to develop a SystemVerilog verification methodology. The result - the VMM methodology - was defined in the book Verification Methodology Manual for SystemVerilog. Over 4,000 copies of the English language edition have been distributed, making it one of the top-selling verification references in print.
VMM Around the World
A standard, well-defined methodology enables geographically dispersed chip development teams to efficiently collaborate on complex verification projects. In 2006, Synopsys and ARM partnered with STARC, a respected research consortium in Japan, to publish a Japanese language edition of the VMM book. In 2007, Synopsys and ARM published a Chinese language edition. These editions of the VMM book make it even easier for large verification teams to work together.
Extending VMM Beyond Base Classes
The SystemVerilog language and the VMM Standard Library provide a stable foundation for methodology innovation. In 2007, Synopsys expanded the scope of the VMM methodology by introducing VMM Applications. VMM Applications are high-level functions that facilitate on-chip register verification, connections to hardware-assisted verification, verification of on-chip memory, and more.