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Registration for VMM-LP Book and Base Class Library Source Code
About the VMM-LP
Based on decades of collective verification and IP experience from ARM, Renesas and Synopsys, the Verification Methodology Manual for Low Power Design (VMM-LP) will document a robust and scalable verification architecture that can be easily leveraged to quickly set up and complete verification of low-power designs. The methodology will address all aspects of functional verification of power-management functions, including suggestions for static versus dynamic verification, design-for-verification techniques, and the use of assertions and coverage metrics to achieve rapid verification closure. The VMM-LP base class library source code will be made available as a free download under the popular Apache 2.0 open source license.

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Thank you for your interest in the VMM-LP. Please complete and submit this registration form to receive updates and information regarding the VMM-LP book and base class library source code.

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