| |
| Resources |
- Technical Papers and Articles
- Leveraging VMM for the SystemVerilog-based verification of cache-based SOC architectures
by Fabien Camus & Jerome Bombal, Texas Instruments France
- Super vmm_data! Automating vmm_data methods in data structures
by Kevin Hyland & Vishal Patel, CréVinn Teoranta
- Progressive migration from ‘e’ to SystemVerilog : A Case Study
by Chris Brown, Dave Wiltshire & Neil Bulman, Texas Instruments Ltd.; Yassine Eben Aimine, Synopsys, Inc.
- VMM For Dummies
by Amre Sultan, Pierre Girodias & Hans van der Schoot, XtremeEDA Corporation
- EE Times India: 'Safari' through SoC verification
by Amit Sharma & SriniVasan Venkataramanan, Synopsys, Inc.
- Are We There Yet?
by Nancy Pratt, IBM; Dwight Eddy, Synopsys, Inc.
- A Fully Reusable Register/Memory Access Solution Using VMM RAL
by Paul Lungu & Bo Zhu, Nortel
- Using Verification IP and VMM Applications to Jumpstart Verification of an AXI Subsystem
by John Dickol, MediaTek Wireless, Inc.
- Techniques for Selective Reuse of Verification Components in Hierarchical Verification of Large Designs
by Tony Tsai, Cisco Systems, Inc.
- Randomized Testbench Development, a Case Study in USB
by Jason Remple, Broadcom Corp.; Denis Bussaglia & Frederic Krampac, Synopsys, Inc.
- Incorporating SystemVerilog and SystemC to Verify Next-Generation Home-Networking Chip
by Ritero Chi, Ho-Ming Leung & Alex Li, Entropic Communications
- Advanced VMM - VMM Register Abstraction Layer Tutorial
- Functional Coverage Techniques: Leveraging Verification IP and VMM for Efficient Testbenches Tutorial
- Extract Maximum Value from Your Verification Plan (VMM Planner)
- Migrating a Large-Scale Vera Testbench Infrastructure to SystemC and SystemVerilog - Risk Mitigation and Value Creation Strategies
by Srinath Atluri, Nimalan Siva & Anant Sakharkar, Cisco Systems Inc.
- Verification IP Reuse for Complex Networking ASICs Using a Hybrid SystemVerilog/ SystemC Environment
by Ben Chen, Srinath Atluri & Harry King, Cisco Systems, Inc.; Shankar Hemmady, Synopsys, Inc.
- Verification of a New IP in Legacy SoC Design using SystemVerilog/VMM
by Asad Khan, Henry Angulo, David Kimble & Paul Howard, Texas Instruments; Jiri Prevratil & Praveen Devulapalli, Synopsys, Inc.
|
|
|
Copyright ©2008. All rights reserved.
|
|
|
|
