http://www.vmmcentral.org/vmartialarts/2009/07/how-to-connect-your-systemc-reference-model-to-your-verification-framework/ A Blog on Verification Methodology Fri, 30 Sep 2011 08:39:43 +0000 hourly 1 http://wordpress.org/?v=3.0.1 http://www.vmmcentral.org/vmartialarts/2009/07/how-to-connect-your-systemc-reference-model-to-your-verification-framework/comment-page-1/#comment-696 System-Level Design » Blog Archive » Blog Review: July 8 Wed, 08 Jul 2009 18:09:34 +0000 http://www.vmmcentral.org/vmartialarts/?p=237#comment-696 [...] Nasib Naser at Synopsys looked at how to link a SystemC model to verification. This is the first stab we’ve seen at this, and it’s a good one, but it probably could turn into a series of books. Modeling is essential at advanced process nodes to allow flexibility in the design—something that will become quite obvious at the first respin—but it’s also going to become a requirement even at older nodes because it can shave time off the design process. [...] [...] Nasib Naser at Synopsys looked at how to link a SystemC model to verification. This is the first stab we’ve seen at this, and it’s a good one, but it probably could turn into a series of books. Modeling is essential at advanced process nodes to allow flexibility in the design—something that will become quite obvious at the first respin—but it’s also going to become a requirement even at older nodes because it can shave time off the design process. [...]

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