Asif Jafri

I am a verification consultant with Verilab Inc since 2009.  I have over 10 years of experience developing testbenches in System Verilog (VMM and OVM), Vera, Verilog, and C++.  Prior to joining Verilab, I was a senior verification engineer at Analog Devices, working on verification of DSP based Soc’s and DSP processors.  I have also worked on the verification of network security processors, Memory controllers and PCI-X bridges.  I hold a MSEE degree from the State University Of New York at Binghamton.