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	<title>Verification Martial Arts &#187; vmm_channel</title>
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	<description>A Blog on Verification Methodology</description>
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		<title>Modeling ISRs with VMM RAL</title>
		<link>http://www.vmmcentral.org/vmartialarts/2010/11/modeling-isrs-with-vmm-ral/</link>
		<comments>http://www.vmmcentral.org/vmartialarts/2010/11/modeling-isrs-with-vmm-ral/#comments</comments>
		<pubDate>Thu, 04 Nov 2010 15:44:28 +0000</pubDate>
		<dc:creator>Amit Sharma</dc:creator>
				<category><![CDATA[Register Abstraction Model with RAL]]></category>
		<category><![CDATA[VMM infrastructure]]></category>
		<category><![CDATA[vmm_channel]]></category>

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		<description><![CDATA[In a verification environment, different components may be trying to access the DUT registers and memories. For example, the BFM might be programming some registers while the bus monitor might be sampling the values of these registers. In specific cases, there may be an interrupt monitor which triggers an Interrupt Service Routine (ISR) whenever it [...]]]></description>
			<content:encoded><![CDATA[<p><font size="2">In a verification environment, different components may be trying to access the DUT registers and memories. For example, the BFM </font><font size="2">might be programming some registers while the bus monitor might be sampling the values of these registers. In specific cases, </font><font size="2">there may be an interrupt monitor which triggers an Interrupt Service Routine (ISR) whenever it sees an Interrupt pin toggling in </font><font size="2">the interface. The ISR might end up having to read the Interrupt registers and end up clearing the Interrupt bit/s through a </font><font size="2">front door access. </font></p>
<p><font size="2">To ensure that different components in a verification environment can access the DUT registers at any given point in time, the RAL </font><font size="2">model instantiated in the environment can be passed to different VMM components. These different components whose methods are </font><font size="2">executing in separate parallel threads can now access the same set of registers in the DUT through the RAL model. A question many </font><font size="2">folks ask is: when there are multiple parallel register accesses, how do they get scheduled through the RAL layer?&#160; Here is an </font><font size="2">explanation of how threads are scheduled in RAL: </font></p>
<p><font size="2">A Register read/write from different threads is comparable to an ‘atomic’ channel.put() from&#160; different threads. Hence it gets </font><font size="2">scheduled in the order of pipelining of the threads.</font></p>
<p><font size="2">A write/read would basically consist of the following atomic operations: </font></p>
<p><font size="2">- A generic <i>vmm_rw_access</i> transaction with its fields (addr, data, kind etc) being populated and posted onto the execute_single() </font><font size="2">&#160; task of the Translate Transactor </font></p>
<p><font size="2">- The transaction being translated in the execute_single() task and pushed into the input channel of the user BFM </font></p>
<p><font size="2">- The transaction being retrieved through get/activate in the User BFM main thread and then subsequently driven to the DUT interface </font></p>
<p><font size="2">Thus ‘posting’ of RAL accesses whenever a Read/Write/Mirror/Update is invoked is in the same order they are issued. Subsequently, </font><font size="2">the <i>execute_single() </i>task just translates the generic RW RAL transaction to a User BFM comprehensible transaction, and doesn&#8217;t </font><font size="2">change the order. </font></p>
<p><font size="2">Now, how do we handle a scenario when specific register accesses like those coming from an ISR need to be given a higher priority </font><font size="2">than accesses coming from other threads in a verification environment?&#160; VMM and RAL methods give us specific hooks to achieve</font><font size="2">this requirement. Here is one of the options on how this can be done. </font></p>
<p><font size="2">If we look at the vmm_ral_reg::write method, we have the given signature:</font></p>
<p><i><font size="2">virtual task write( output vmm_rw::status_e status, </font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input bit [63:0] value, </font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input vmm_ral::path_e path = vmm_ral::DEFAULT, </font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input string domain = &quot;&quot;,</font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input int data_id = -1,</font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input int scenario_id = -1,</font></i></p>
<p><i><font size="2">&#160;&#160;&#160; input int stream_id = -1)</font></i></p>
<p><i></i></p>
<p><font size="2">Now, a generic RAL transaction that gets created through any Register access has the same data_id, scenario_id, stream_id arguments which get passed on from the read/write call. These arguments help us tag and track the transactions if that is so desired. Now, these arguments can be made use of in the execute_single() task to ensure that accesses from ISRs have the highest priority. But, first, if we go back to the earlier post by <a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvcy12YXJ1bi8=">Varun</a>, Issuing concurrent READ/WRITE accesses to the same register on two physical interfaces using RAL, <a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvMjAxMC8wOC9pc3N1aW5nLWNvbmN1cnJlbnQtcmVhZHdyaXRlLWFjY2Vzc2VzLXRvLXRoZS1zYW1lLXJlZ2lzdGVyLW9uLXR3by1waHlzaWNhbC1pbnRlcmZhY2VzLXVzaW5nLXJhbC0yLw==">Issuing concurrent accesses to the same registers on two physical interfaces using RAL</a>&#160;</font><font size="2">, we note that if the RAL model is processing a ‘register access’ , it will not initiate the next one until the earlier one is completed. So, this is what we need to get done.We first use the RAL Proxy transactor to schedule the ISR register access simultaneously. After that, we flush out any existing accesses and prevent any new register access through RAL until access from the ISR is completed</font></p>
<p>This is how it, will be done:</p>
<p><a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvd3AtY29udGVudC91cGxvYWRzLzIwMTAvMTEvaW1hZ2UxLnBuZw=="><img style="border-right-width: 0px;float: none;border-top-width: 0px;border-bottom-width: 0px;margin-left: auto;border-left-width: 0px;margin-right: auto" border="0" alt="image" src="http://www.vmmcentral.org/vmartialarts/wp-content/uploads/2010/11/image_thumb1.png" width="514" height="349" /></a> </p>
<p><font size="2"></font></p>
<p><font size="2">For a normal register access, a read/write method will be invoked as follows:</font></p>
<p><font size="2"><i>&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; ral_model.&lt;reg_name&gt;.write(stat,wdata, “AHB”);</i> //’wdata’ is the value to be driven, “AHB” is the domain /physical interface</font></p>
<p><font size="2">For a register access in an ISR modeled in a MS Scenario, we have:</font></p>
<p><font size="2"><i>&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; env.bfm.to_ahb.grab(this); //</i><b><i>grabs the channel</i></b><i> </i></font></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; env.ral.read(status, env.ral_model.&lt;reg_name&gt;.get_address_in_system(&quot;AHB&quot;), </font></i><i><font size="2">data, 32, &quot;AHB&quot;,,,1); // The last argument is again the “stream_id” argument</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; env.bfm.to_ahb.ungrab(this); //<b>allows the channel to be accessed from other threads once the ISR is completed</b></font></i></p>
<p> <i></i><i></i><i></i>
<p><font size="2">Once, this is done, the execute_single() task inside the translate Transcator will know if an access is through an ISR and can ensure that ISRs are processed on priority through a combination of functionality provided through the VMM Channel methods in combination with a semaphore:</font></p>
<p> <i></i>
<p><i><font size="2">virtual task execute_single(vmm_rw_access tr);</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; AHB_tr cyc;</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; AHB_tr cyc_active; //<b>to keep any transactions residing on the active slot</b></font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; semaphore sem = new(1); //<b>semaphore with a single key to prevent new accesses when a reg access from an ISR is processed</b></font></i></p>
<p> <i></i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160; // Translate the generic RW into a simple RW</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160; cyc = new;</font></i></p>
<p><em><font size="2">&#160;&#160;&#160;&#160;&#160;&#160; {cyc.dev, cyc.addr} = tr.addr;</font></em></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160; if (tr.kind == vmm_rw::WRITE) begin</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; cyc.cycle = simple_tr::WRITE;</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; cyc.data = tr.data;</font></i></p>
<p>&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; &#8230;</p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160; end</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; else begin</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; cyc.cycle = simple_tr::READ;</font></i></p>
<p>&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; &#8230;</p>
<p>&#160;&#160;&#160;&#160;&#160; <i><font size="2">end</font></i></p>
<p> <i></i>
<p><i><font size="2"><b>&#160;&#160;&#160;&#160;&#160; if (tr.stream_id != 1) sem.get(1)</b>; // <b>regular register access gets blocked here when a reg access from an ISR is processed</b></font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; else begin</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; if(this.bfm.to_ahb.is_full()) begin</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.bfm.to_ahb.activate(cyc_active); //<b>removes any existing transactions in the channel’s active slot so that the current access can be pushed through</b></font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.in_chan.start();</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.in_chan.complete();</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.in_chan.remove();</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.bfm.to_ahb.put(cyc);</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; this.bfm.to_ahb.put(cyc_active); //<b>restores the original transaction back into the active slot</b></font></i></p>
<p> <i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; cyc = cyc_active;</font></i></p>
<p> </i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; sem.put(1); //<b>ths ISR access puts back the key for normal accesses to resume</b></font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; end</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; else this.bfm.to_ahb.put(cyc);</font></i></p>
<p> <i></i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; end</font></i></p>
<p> <i></i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; // Send the result back to the RAL</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; if (tr.kind == vmm_rw::READ) begin</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160;&#160;&#160; tr.data = cyc.data;</font></i></p>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; end</font></i></p>
<p> <i></i>
<p><i><font size="2">&#160;&#160;&#160;&#160;&#160; endtask: execute_single</font></i></p>
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		<title>Controlling transaction generation timing from the driver using &#8216;PULL&#8217; mode</title>
		<link>http://www.vmmcentral.org/vmartialarts/2010/07/controlling-transaction-generation-timing-from-the-driver-using-pull-mode/</link>
		<comments>http://www.vmmcentral.org/vmartialarts/2010/07/controlling-transaction-generation-timing-from-the-driver-using-pull-mode/#comments</comments>
		<pubDate>Fri, 30 Jul 2010 08:23:12 +0000</pubDate>
		<dc:creator>Amit Sharma</dc:creator>
				<category><![CDATA[Communication]]></category>
		<category><![CDATA[Stimulus Generation]]></category>
		<category><![CDATA[vmm_channel]]></category>

		<guid isPermaLink="false">http://www.vmmcentral.org/vmartialarts/?p=1728</guid>
		<description><![CDATA[Sadiya Tarannum Ahmed, Senior CAE, Synopsys In the default flow, the transaction level communication in VMM Channels operates in the ‘PUSH’ mode, i.e., the process is initiated by the producer which randomizes and pushes a transaction in the channel when it is empty. This process is repeated again when the channel is empty or the [...]]]></description>
			<content:encoded><![CDATA[<p><strong>Sadiya Tarannum Ahmed</strong>, Senior CAE, Synopsys</p>
<p>In the default flow, the transaction level communication in VMM Channels operates in the ‘PUSH’ mode, i.e., the process is initiated by the producer which randomizes and pushes a transaction in the channel when it is empty. This process is repeated again when the channel is empty or the consumer retrieves the transaction from the channel. However, in specific cases, you might not want the generator to create stimulus before the bus protocol is ready or until it is requested by the bus-protocol. In this case, you may want to use the ‘PULL’ mode in VMM channels.</p>
<p>In ‘Pull’ mode, the consumer initiates the process by requesting transactions and then the generator or the producer responds to it by putting the transaction into the channel.</p>
<p>&#160;</p>
<p>&#160;<a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvd3AtY29udGVudC91cGxvYWRzLzIwMTAvMDcvaW1hZ2UucG5n"><img style="border-right: 0px;border-top: 0px;border-left: 0px;border-bottom: 0px" height="268" alt="image" src="http://www.vmmcentral.org/vmartialarts/wp-content/uploads/2010/07/image_thumb.png" width="564" border="0" /></a></p>
<p><a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvd3AtY29udGVudC91cGxvYWRzLzIwMTAvMDcvaW1hZ2UxLnBuZw=="></a></p>
<p><a href="http://www.vmmcentral.org/vmartialarts/wp-content/plugins/feed-statistics.php?url=aHR0cDovL3d3dy52bW1jZW50cmFsLm9yZy92bWFydGlhbGFydHMvd3AtY29udGVudC91cGxvYWRzLzIwMTAvMDcvaW1hZ2UxLnBuZw=="></a></p>
<p>The following steps show how the communication can operate in “PULL_MODE”. </p>
<p>Step1: In the generator code, call the vmm_channel::wait_for request() method before randomizing and putting the transaction into the channel. </p>
<p>By default vmm_channel::wait_for_request() does not block (“PUSH MODE”). In “PULL” mode, it will block<ins cite="mailto:amits" datetime="2010-07-13T14:12"> </ins>until a get/peek/activate() is invoked by the consumer</p>
<p>class cpu_rand_scenario extends vmm_ms_scenario;   <br />&#160;&#160; &#8230;    <br />&#160;&#160; cpu_trans blueprint;    <br />&#160; `vmm_scenario_new(cpu_rand_scenario)    <br />&#160;&#160; &#8230;    <br />&#160;&#160; &#8230;    <br />&#160;&#160; virtual task execute(ref int n);    <br />&#160;&#160;&#160;&#160;&#160;&#160; blueprint = cpu_trans::create_instance(this, &quot;blueprint”);    <br /><b><i>&#160;&#160;&#160;&#160;&#160;&#160; chan.wait_for_request();       <br /></i></b>&#160;&#160;&#160;&#160;&#160;&#160; assert(blueprint.randomize());    <br />&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160; else `vmm_fatal(log, “cpu_trans randomization failed”);    <br />&#160;&#160;&#160;&#160;&#160;&#160; chan.put(blueprint.copy());    <br />&#160;&#160;&#160;&#160;&#160;&#160; n++;    <br />&#160;&#160; endtask     <br />&#160; &#8230;    <br /> `vmm_class_factory(cpu_rand_scenario)    <br />endclass </p>
<p>Step2: Set the mode of channels.</p>
<p>By default, all channels are configure to work in “PUSH_MODE” and can be set to work in “PULL_MODE” statically or dynamically.</p>
<ul>
<li>·Static setting: Set the mode of channel in the testbench environment or in your testcases</li>
</ul>
<p>&#160;&#160;&#160;&#160;&#160; gen_to_drv_chan.set_mode(vmm_channel::PULL_MODE);</p>
<ul>
<li>Dynamic: call the Runtime switch +vmm_opts+pull_mode_on</li>
</ul>
<p>Since the mode can be changed through vmm_opts, hierarchical or instance based setting for any channel can also be done at runtime. This brings in a lot of flexibility and the same channel can be made to work under different modes for different tests or even within the same simulation</p>
<p>The pre-defined atomic and scenario generators now support this feature; which can either be enabled by runtime control or by setting the associated channel mode to PULL_MODE in the environment.</p>
<p>Thus you now have the flexibility to configure your transaction level communication easily based on your requirements.</p>
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