Parag Goel
I am a Senior Corporate Application Engineer at Synopsys. I currently focus on advanced methodologies, like VMM and UVM, and am also involved in DesignWare Verification IP development, providing solutions to key customers. Over the past 5 years, I was primarily into ASIC verification using HVLs such as SystemVerilog, and verification methodologies at Transwitch and Applied Micro. I played a key role in the development of verification IP for various standard protocols, especially related to Ethernet switching and AMBA related protocols – AXI/AHB. I also worked on module-level PCI Express verification and PPC side verification in the SoC environment.
