"LP verification is the key challenge in LP design. VMM-LP helps create a reusable verification environment for LP that can leverage best
practices from industry experts. It helps find LP bugs and finds them early in the design cycle rather than waiting for silicon - savings in
terms of mask costs, engineering debug time can be huge."
Hisilicon K3 LP Group
"We see a prevalence of low power designs in Japan and a strong need for a comprehensive verification methodology to tape out such designs
with confidence. VMM-LP is the answer to this market need and completely and elegantly addresses all aspects of low power verification.
The book covers what is needed to verify low power designs and get it right - the first time around."
Vice President and General Manager, Development Department 1
STARC (Semiconductor Technology Academic Research Center)
"The task of
verifying low power designs
presents a significant challenge
for today's verification engineers,
as most are not yet well-trained
on low power concepts. The
Verification Methodology Manual
for Low Power is a timely
and valuable resource that
addresses all aspects of low
power verification, providing
detailed rules and guidelines."
Senior Low Power Verification Methodology Engineer
"Because power consumption is one of the most critical factors of today’s SoCs for mobile applications, the ability to accurately verify low
power functionality is essential to achieving first-pass silicon success. The Verification Methodology Manual for Low Power is a comprehensive
collection of necessary and reliable techniques that should help simplify and accelerate the complex task of verifying power-managed designs."
Technical Director of Home Entertainment Products
"Low power has been elevated to a primary design consideration and companies have been forced to deal with the complex verification issues
associated with these design practice without much in the way of tool or methodology help. This book provides a key piece of that solution,
with very helpful guidance that not only builds upon the existing VMM, but provides a firm foundation into sound techniques to ensure that
no problems exist in the power control circuitry."
Independent Functional Verification and ESL Consultant
"Being able to create a power control architecture is more than just having something that looks pretty on paper and, theoretically, meets your
power targets. The VMM-LP provides clear insight into the pitfalls and practicality issues for both the design and verification of low power
systems. This handy volume comes with specific examples of design and verification issues that have been seen in actual chips. Its rules and
recommendations will help move the electronics industry into a much greener future."
SoC Power Architect
"Low power requirements have caused a paradigm shift for the entire semiconductor ecosystem. Lacking an open, codified and documented methodology,
accurate and comprehensive verification of low power designs has been a black art and a productivity drain. With its methodical and guidebook
style approach, the VMM-LP provides a clear blueprint for successful verification of low-power designs - this one is a keeper."
Dr. Ed Huijbregts
Vice President of Product Development
Magma Design Automation