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In these short but informative videos, you hear the authors of the Verification Methodology Manual (VMM-LP) talk about the challenges of low power verification, the methodology documented in the VMM-LP book and how the VMM-LP helps engineers accomplish the difficult task of verifying low power designs.
David Flynn, Fellow, ARM
Srikanth Jadcherla, Group R&D Director, Synopsys
Janick Bergeron, Fellow, Synopsys
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