Webinar on Deploying UVM Effectively
Posted by Shankar Hemmady on October 22nd, 2012
Over the past two years, several design and verification teams have begun using SystemVerilog testbench with UVM. They are moving to SystemVerilog because coverage, assertions and object-oriented programming concepts like inheritance and polymorphism allow them to reuse code much more efficiently. This helps them in not only finding the bugs they expect, but also corner-case issues. Building testing frameworks that randomly exercise the stimulus state space of a design-under-test and analyzing completion through coverage metrics seems to be the most effective way to validate a large chip. UVM offers a standard method for abstraction, automation, encapsulation, and coding practice, allowing teams to build effective, reusable testbenches quickly that can be leveraged throughout their organizations.
However, for all of its value, UVM deployment has unique challenges, particularly in the realm of debugging. Some of these challenges are:
- Phase management: objections and synchronization
- Thread debugging
- Tracing issues through automatically generated code, macro expansion, and parameterized classes
- Default error messages that are verbose but often imprecise
- Extended classes with methods that have implicit (and maybe unexpected) behavior
- Object IDs that are distinct from object handles
- Visualization of dynamic types and ephemeral classes
Debugging even simple issues can be an arduous task without UVM-aware tools. Here is a public webinar that reviews how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.