Verification Martial Arts: A Verification Methodology Blog

Ashok Chandran

Over the past three years at Analog Devices, I have been  actively involved in design, verification and post-silicon activities for DSP processors.  I was responsible for bring up of a new re-usable SystemVerilog VMM testbench architecture and coverage driven closure at SoC level.  Prior to Analog Devices, I was responsible for unit level verification of Passive Optical Network chips at Conexant.

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