Verification Martial Arts: A Verification Methodology Blog

Bagath Singh

I am Verification Lead at CVC, Bangalore, India. I have been working in VLSI front end Design and Verification for the past 4 years. I have developed few communication protocol VIPs with different methodologies in SystemVerilog and E. My interests are the advanced verification solutions and methodologies such as SystemVerilog, VMM, and my favorite domain is networking.