Verification Martial Arts: A Verification Methodology Blog

Jaya Chelani

I am a senior design verification engineer at Quartics Technologies, currently working on next generation multimedia accelerator designs. Over the past two years, my specific focus is on building and executing robust, reusable and maintainable verification environments for our series of products using SystemVerilog with VMM. Earlier, I was a design engineer at Connexant and Alliance Semiconductor.

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