JL Gray is a Vice President with Verilab, Inc. based in Austin, Texas, and author of Cool Verification. Since joining Verilab in 2004, he has consulted extensively in verification planning, methodology development, and project execution with a wide range of clients in Europe, Asia, the Middle East, and the US. JL has presented workshops on verification methodology and planning around the world. He has also implemented verification environments in all of the major e and SystemVerilog libraries (eRM, VMM, and OVM) and he led Verilab’s effort to develop the multi-stream scenario capabilities in the Synopsys VMM 1.1 released in December 2008.
In addition to his consulting activities, JL has contributed to the EDA industry as Verilab’s representative on the Accellera Verification IP Technical Subcommittee. He has also worked extensively on the application of social media to the EDA industry as a means of fostering collaboration in the wider engineering community. JL is well known in the Electronic Design Automation (EDA) industry as the author of Cool Verification, a blog about hardware verification from a consultant’s perspective.
Prior to joining Verilab, JL was one of the first verification engineers at ServerEngines where he created a verification environment using SystemC. He also spent 5 years at Intel , where he developed verification environments and methodologies using Specman for 1G and 10G Ethernet controllers.
JL has a BSEE from Purdue University in West Lafayette, Indiana. He can be reached at jl dot gray at verilab dot com.