I design & verify complex ASICs at Brocade. Over the past four years, I have been an ASIC front-end design, verification & modelling engineer. I have worked on multimedia, processor and networking chips. Earlier in my career, I began with TCL, later moved to Verilog and C++. I now extensive use SystemVerilog with VMM. By sharing my experiences, I feel I make my small contribution to advance best practices in ASIC design and verification.