Verification Martial Arts: A Verification Methodology Blog

Puja Sethia


As ASIC Verification Technical Lead at eInfochips, I am responsible for executing verification projects. I have worked on verification of complex networking chips as well as tester chip application using System Verilog, C++ and SystemC, starting from defining architecture to verification closure. I have also developed various assertion IP’s and verification IP’s.  I enjoy developing automated verification environments.

One Response to “Puja Sethia”

  1. Dayananda Says:

    Hi, I have gone through many of your articles in Verification including SNUG papers. Good Contribution to verification society!! Keep up the spirit.

    - Daya

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