- Verification Methodology Manual for Low Power [Purchase hard copy]
- Verification Methodology Manual for Low Power [Download PDF]
- Low Power Methodology Manual
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This tutorial on the Verification Methodology Manual for Low Power (VMM-LP) features authors of the book discussing the complexities and changes brought about in the low power era and the ways in which the VMM-LP can help you achieve comprehensive verification of increasingly complex low power designs.
|VMM-LP Author Interviews|
|In these short but informative videos, you hear the authors of the Verification Methodology Manual (VMM-LP) talk about the challenges of low power verification, the methodology documented in the VMM-LP book and how the VMM-LP helps engineers accomplish the difficult task of verifying low power designs.|
|David Flynn, Fellow, ARM|
|Srikanth Jadcherla, Group R&D Director, Synopsys|
|Janick Bergeron, Fellow, Synopsys|
- Low Power Design Portal: Experts from the VMM for Low Power
- EE Times: Why voltage-aware verification strategy counts
- New Electronics: Low power verification methodology: Is this a case of natural evolution?
- EDACafe: Power and Verification Always Matter [A review of the VMM-LP book]
- EDN: Chip-verification and -design flow focus on low power
- EDN: Verification methodology for low power: Your blueprint to working silicon
- EE Times: Boost verification accuracy with low-power assertions
- Chip Design: A Ticking Time Bomb?
- Chip Design: Coding Practices Adapt to a Low-Power World