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A Fully Reusable Register/Memory Access Solution Using VMM RAL
by Paul Lungu & Bo Zhu, Nortel

Register structure and memory modeling is an extremely complex task in any verification methodology. Building a zero time mirror to check the correct functionality of every field from every register and memory is usually a very time-consuming process, which needs to be repeated for every design. This paper describes a new approach in resolving this issue by using the VMM Register Abstraction Layer (RAL).
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